Electrostatic discharge (ESD) is a known problem in the manufacturing and using of integrated circuits. Typically, integrated transistors have thin oxides and insulating layers that can be damaged by the electrostatic discharge, and special care is required to protect the integrated circuits from the damage caused by ESD.
As device sizes continue to shrink, the damage occurring to transistors and caused by ESD pulses becomes increasingly more severe. The integrated circuits coupled between VDD and VSS nodes cannot handle the relatively large current in short time and the integrated circuits may be damaged. FIG. 1 illustrates an exemplary circuit including a pad for input or output, a VDD node, a VSS node, and a power clamp coupled between the VDD node and the VSS node. The power clamp includes NMOS transistors N1 and N2 that are cascaded between the VDD node and the VSS node. NMOS transistors N1 and N2 may be low nominal VDD devices, which means that the maximum allowable gate-to-source or the maximum gate-to-drain voltage for each of NMOS transistors N1 and N2 is lower than voltage VDD. If the gate-to-source or the gate-to-drain voltages are greater than voltage VDD, NMOS transistors N1 and N2 will be damaged. The parasitic bipolar transistor BP, which is formed between the drain of NMOS transistor N1, the source of NMOS transistor N2, and the substrate of the respective chip, acts as the ESD device that becomes conductive to conduct ESD currents.
The power clamp in FIG. 1 has a high ESD trigger voltage equal to or higher than about 8.5V. However, the circuit that is to be protected by the power clamp, such as the schematically illustrated inverter INV, also has a parasitic bipolar transistor (not shown) that will be turned on to conduct the ESD current at a trigger voltage equal to about 7.1V. This means that the protected circuit may be turned on before the activation of the power clamp. Since the protected circuit is not designed to handle the relatively high ESD current, it may be damaged, and the power clamp fails to protect the circuit that it is designed to protect.